A 30-ps jitter, 3.6-/spl mu/s locking, 3.3-volt digital PLL for CMOS gate arrays

摘要: A 3.3-V digital phase-locked loop (DPLL) with a 30-ps jitter resolution and 3.6-/spl mu/s locking time has been developed to support 0.65-/spl mu/m CMOS gate array. The innovative DPLL features dual-mode automatic control logic for coarse fine locking, autorecovery circuitry compensate failure due substantial system clock drift, nominal 200-/spl mu/W power dissipation. Multiple DPLLs can be utilized in each array clocks of above 100 MHz. Low-power operation is accomplished no DC-current-consuming circuitry, order better serve portable applications. high-resolution instances are allowed on virtually any spot the die, either or 5-V operation. System reliability enhanced by implementation which monitors faults caused poor environmental control.