System for distributing clocks using a delay lock loop in a programmable logic circuit
作者： L. Todd Cope , Richard G. Cliff , Srinivas Reddy , David E. Jefferson
DOI:
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摘要: A system (100) for distributing a clock signal to many points on an integrated circuit. The includes using delay lock loop with specific digital circuits accomplish the phase error detection and element selection. In one embodiment, two flip-flops are used detect error. another both macro (202) micro detectors (218) selection is performed in stages by shift register (210) first stage counter (220) second stage. Another feature of present invention is, ability distribute reference or synchronized different portions circuitry Multiple distribution systems provided which may be selected.
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