Phase-locked loop for MFM data recording

摘要: A phase-locked loop (PLL) for use in decoding MFM data recordings. The uses a counter to generate timing signals which divide bitcells into and clock windows define times within these at transitions the signal are expected occur. Data of differing relative size readily accomodated. PLL has two synchronization modes: one mode allows take maximum advantage both occur when reading actual data; second is used during period beginning block lock quickly yet assure that it will bit frequency not harmonics or beat frequencies. charge pump generates error by responding pump-up pump-down control set cleared response from detection input signal. While mode, transition occurs after time storage circuit over dynamics. includes VCO with an automatic dynamic adjustment VCO's center accomplished adjusting reverse bias voltage on diode functions as capacitor VCO. This make maximal range.