Digital delay lock loop for clock signal frequency multiplication

作者: Chris Lane

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摘要: A digital delay lock loop for generating frequency multiples of an input clock signal includes a programmable oscillator, phase comparator, counter and control logic. The oscillator is ring connected line inverter which together generate output having depends upon the time line. comparator compares to that reference generates error represents difference between such signals. counter, programmed reprogrammed with arrival every pulse, counts pulses count signal. logic, in response signal, programs line, thereby causing be desired multiple frequency.

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