***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***System and method to improve the efficiency of synchronous mirror delays and delay locked loops
作者： Feng Lin
DOI:
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摘要: A phase detection system for use with a synchronous mirror delay or delay-locked loop in order to reduce the number of stages required, and therefore increase efficiency, is disclosed. The invention includes taking clock input signal feedback signal, each having timing characteristics, differentiating between four conditions based upon characteristics signals. detector associated circuitry then determines, signals, which signals are in. Selectors select be introduced into by conditions. able utilize falling edge lock time decreased under specific increases efficiency circuits reducing effective SMD DLL while maintaining operating range.
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