Adaptive lock time controller for a frequency synthesizer and method therefor

摘要: An adaptive lock time controller for a phase locked loop having dividers generating first and second timing signals, detector, voltage controlled oscillator, charging circuit at least control signal converging the output frequency to one or more predetermined channels maintaining substantially constant, comprises synchronization generator, selector. The generator is responsive detector synchronizing detector. detects unlocked conditions by count representative of difference between signals. When generated exceeds count, condition exists, otherwise unlocked. selector selects during interval when detected, detected.