Direct memory access controller with interface configured to generate wait states
作者： Byron R. Gillespie , Mark A. Yarch , Marc A. Goldschmidt
DOI:
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摘要: A computer system is provided including a local memory, bus coupled to the peripheral and direct memory access (DMA) controller. The DMA controller performs transfers of data between bus. includes queue for storing be transferred ownership status circuit determining further interface halting transfer from without relinquishing over when full indicates that has both
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