System and method for power management in a java accelerator environment
作者： Bonnie Sexton , David Envoy , Lonnie Goff
DOI:
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摘要: A power management method is disclosed which provides for a hardware based Java accelerator. Initially, mode signal provided from host processor in response to initiating application. Thereafter, the reduced, and increased signal. Then, when execution of application halts, completion generated processor, thus signaling system return control back processor.
google.com.mx参考文章(26)
Mark E. Miller, Kenneth E. Garey, Microprocessor system with flexible instruction controlled by prior instruction ,(1995)
James C. Boyd, Circuit for reducing power consumption in battery operated microprocessor based systems ,(1978)
Hermann Mayer, Hermann Winner, Manfred Hellmann, Ralph Lauxmann, Method and device for monitoring a computer system comprising at least two processors ,(1998)
Su Shion Huang, Portable computer with dual switchable processors for selectable power consumption ,(1998)
Peter T. McLean, Adaptive power management for hard disk drives ,(1994)
David Ross Evoy, Paul S. Levy, Stack cache for stack-based processor and method thereof ,(1996)
Douglas M. Carmean, John Crawford, A cache coherent multiprocessing computer system with reduced power operating features ,(1995)
Ronald Jason Barber, Edwin Joseph Selker, Sleep mode transition between processors sharing an instruction set and an address space ,(1998)
Prasad Raje, Rajiv Gupta, Microprocessor having software controllable power consumption ,(1995)
William Preston Alexander, Weiming Gu, Process and system for Java virtual method invocation ,(1999)