System and method for hierarchical device extraction

作者: Eric Rogoyski

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摘要: A device extractor (120) for extracting devices from a hierarchical cell design (206). The selects the lowest level of hierarchy and searches components. each in then "parent" penultimate level. parent cell, all children cells are searched. selection search process continues until components (208) identified or proper relationship between is determined. masked so that they not associated with another during subsequent searches.

参考文章(11)
Manmohan Mittal, Hierarchical netlist extraction tool ,(1992)
L.G. Chen, J.Y. Lee, J.F. Wang, Hierarchical functional verification for cell-based design styles IEE Proceedings G Circuits, Devices and Systems [see also IEE Proceedings-Circuits, Devices, and Systems]. ,vol. 134, pp. 103- 110 ,(1987) , 10.1049/IP-G-1.1987.0014
J. Yoshida, Y. Goto, T. Ozaki, PANAMAP-B: A Mask Verification System for Bipolar IC design automation conference. pp. 690- 695 ,(1981) , 10.5555/800073.802376
N. Hedenstierna, K.O. Jeppson, The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 12, pp. 265- 272 ,(1993) , 10.1109/43.205006
Anton G. Salecker, Allen Baisuck, Richard L. Fairbank, Walter K. Gowen, Eric Rogoyski, Judith A. Huckabay, William W. Hoover, Jon R. Henricksen, System and method for model-based verification of local design rules ,(1995)
Shigeru Shimada, Michael Saniei, Balaji Krishnamachary, Method of extracting parameters for circuit simulation ,(1993)
Anton G. Salecker, Allen Baisuck, Richard L. Fairbank, Walter K. Gowen, Eric Rogoyski, Jon R. Henriksen, Judith A. Huckabay, William W. Hoover, Data reduction in a system for analyzing geometric databases ,(1994)