作者: Luca Vanzolini , Antonio Deledda , Matteo Pizzotti , Andrea Lodi , Fabio Campi
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摘要: This paper describes a digital signal processor based on multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized CMOS 090 nm technology. most relevant features offered by the proposed architecture with respect to state of art are zero over head switching between successive configurations, area and energy computational density kernels (average 2 GOPS/mm2, 0.2GOPS/mW) relatively small occupation (18 mm2), making it acceleration or upgrade multi-core heterogeneous embedded platforms. is delivered software tool chain providing application developer algorithmic analysis space exploration ANSI C, no utilization hardware-related constructs description languages.