作者: Pablo Abad , Valentin Puente , José Angel Gregorio , Pablo Prieto
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摘要: The trend towards increasing the number of processor cores and cache capacity in future Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection networks adapted to restrictions imposed by CMP environment. This paper presents an innovative router design, which successfully addresses cost/performance constraints. structure is based on two independent rings, force packets circulate either clockwise or anti-clockwise, traveling through every port router. It uses a completely decentralized scheduling scheme, allows design to: (1) take advantage wide links, (2) reduce Head Line blocking, (3) use adaptive routing, (4) be topology agnostic, (5) scale with network degree, (6) have reasonable power consumption implementation cost. A thorough comparative performance analysis against competitive conventional routers shows for our proposal up 50 % terms raw nearly 60 energy-delay product.