Packet router for multiprocessor systems.
作者： Valentín Puente Varona , Pablo Abad Fidalgo , José Ángel Gregorio Monasterio
DOI:
关键词:
摘要: The invention relates to a packet router for the interconnecting networks of multiprocessor system. comprises 2·B basic building blocks (101, 102, 103, 104) arranged in ring around local node (100), wherein B is natural number greater than 1. configured such that each enters flows through loop passes until it reaches an output port directs same its destination. Each block (101) reception stage (RECEPTION), ejection (EJECTION) and FIFO buffer (DFIFO), which (DFIFO) has two input ports (R3, Li) (E3, Lo). One (R3) connected while other (Li) front-end (104). Moreover, one (E3) (EJECTION), (Lo) back-end (102). that: either leaves via or aforementioned (102) so can continue loop.
lens.org 参考文章(3)
Pablo Abad, Valentin Puente, José Angel Gregorio, Pablo Prieto, Rotary router Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07. ,vol. 35, pp. 116- 125 ,(2007) , 10.1145/1250662.1250678
Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das, MIRA ACM SIGARCH Computer Architecture News. ,vol. 36, pp. 251- 261 ,(2008) , 10.1145/1394608.1382143
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh, Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP) symposium on computer architecture and high performance computing. pp. 211- 218 ,(2007) , 10.1109/SBAC-PAD.2007.38