摘要: MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts signals with aim minimizing circuit area. Our range technique identifies number bits required. For precision analysis, we employ a semi-analytical analytical error models in conjunction adaptive simulated annealing find optimum bits. Improvements given design reduce area latency by up 20% 12% respectively, over uniform Xilinx Virtex-4 FPGA.
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