作者: Robert Rutten , Lucien J. Breems , Gunnar Wetzker
DOI: 10.1109/ESSCIR.2006.307565
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摘要: This paper presents a digital calibration system for continuous-time cascaded ΣΔ modulator. The algorithm matches the noise cancellation filter coefficients with integrator time constants of analog loop filters, resulting in an optimal signal-to-quantization ratio. method that is proposed based on two-point variance estimation idling output data stream when zero input signals are applied. highly insensitive to large spread variance, due pseudo random nature main advantages this very high accuracy and fast speed, while additional hardware costs negligible. A 0.18mum CMOS prototype test chip has been fabricated measured 0.6ms 10MHz, 67dB dynamic range