作者: Subhanshu Gupta , Yi Tang , Jeyanandh Paramesh , David J. Allstot
DOI: 10.1007/S11265-012-0677-3
关键词:
摘要: A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. 22-dB amplifier relaxes design constraints analog front-end (AFE). The integrator non-idealities in AFE sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. proposed half- (f s/2) and quarter-rate s/4) LMS schemes reduce computational complexity achieve more than 2.5× savings digital power consumption low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders sampling frequencies. scheme can have further applications serial-link I/O sub-band echo cancellation architectures.