Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs

作者: Subhanshu Gupta , Yi Tang , Jeyanandh Paramesh , David J. Allstot

DOI: 10.1007/S11265-012-0677-3

关键词:

摘要: A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. 22-dB amplifier relaxes design constraints analog front-end (AFE). The integrator non-idealities in AFE sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. proposed half- (f s/2) and quarter-rate s/4) LMS schemes reduce computational complexity achieve more than 2.5× savings digital power consumption low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders sampling frequencies. scheme can have further applications serial-link I/O sub-band echo cancellation architectures.

参考文章(15)
Gabor C Temes, Richard Schreier, Shanti Pavan, Understanding Delta-Sigma Data Converters ,(2004)
Alan V. Oppenheim, Ronald W. Schafer, Discrete-Time Signal Processing ,(1989)
B. Murmann, Digitally Assisted Analog Circuits IEEE Micro. ,vol. 26, pp. 38- 47 ,(2006) , 10.1109/MM.2006.33
Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song, LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators IEEE Journal of Solid-state Circuits. ,vol. 45, pp. 368- 379 ,(2010) , 10.1109/JSSC.2009.2036759
Noha Younis Ahmed, Mahmoud Aly Ashour, Amin Mohamed Nassar, Power efficient polyphase comb decimation filters for ΣΔ modulators in multi-rate digital receivers european conference on circuit theory and design. pp. 719- 722 ,(2009) , 10.1109/ECCTD.2009.5275093
Robert Rutten, Lucien J. Breems, Gunnar Wetzker, Digital Calibration of a Continuous-Time Cascaded ΣΔ Modulator based on Variance Derivative Estimation european solid-state circuits conference. pp. 199- 202 ,(2006) , 10.1109/ESSCIR.2006.307565
G. Cauwenberghs, G.C. Temes, Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 47, pp. 621- 628 ,(2000) , 10.1109/82.850421
Charles T. Peach, Un-Ku Moon, David J. Allstot, An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$ m CMOS IEEE Journal of Solid-state Circuits. ,vol. 45, pp. 391- 400 ,(2010) , 10.1109/JSSC.2009.2038123