Power-on initializing circuit
作者： Jeffrey E. Smith , Roshan J. Fernando , Keng L. Wong , Gregory F. Taylor
DOI:
关键词:
摘要: A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, initialization is included circuit. In response receiving Vcc, generates a substitute clock signal reset signal. The are substituted off chip generated power-up until predetermined condition met. signal, plurality circuits on said initialized.
lens.org 参考文章(26)
Shinichi Tanaka, Voltage detection circuit composed of at least two MOS transistors ,(1977)
Minru Lee, Clock selection circuit ,(1989)
Chikahiro Hori, Hiroyuki Watanabe, Clock buffers arranged in a peripheral region of the logic circuit area ,(1990)
Vernon Knowles, Rajeev Badyal, CMOS power-on reset circuit ,(1994)
Kenneth A. Poteet, Duy-Loan T. Le, Scott E. Smith, Duc Ho, Fuse selectable timing signals for internal signal generators ,(1993)
Tutomu Nakamori, CMOS power-on reset pulse generating circuit with extended reset pulse duration ,(1983)
Takashi Toyooka, Mamoru Sugie, Hirokazu Aoki, Shinsaku Chiba, Kazutoshi Yoshida, Reset signal generating circuit ,(1983)
Ching-Tung Hwang, Hsiang-Hsing Sung, Clock switching circuit and method for preventing glitch during switching ,(1991)
Fukuo Sekiya, Shigeru Morokawa, Solid state binary logic signal source for electronic timepiece or the like ,(1975)
Hugn-Chyuan Hsieh, Chieh-Chih Yu, Circuit for initializing registers using two input signals for writing default value into D-latch after a reset operation ,(1990)