Phased nand power-on reset

作者: Farookh Moogat , Alexander Kwok-Tung Mak , Steven S. Cheng , Dennis Ea , Jianmin Huang

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摘要: A method and system for phasing power-intensive operations is disclosed. non-volatile storage device controller detects a power reset. The in communication with non- volatile memories the device. In response to detecting reset, determines current consumption necessary reset simultaneously resets all of when determined less than threshold. If greater threshold, first subset plurality memories, after predetermined delay, second memories. Therefore, operation may be performed without exceeding threshold by dividing into sequence steps that do not exceed

参考文章(10)
Brigitte Hennebois, Serge Monari, Jean-Yves Monari, heir by Philippe Monari, heirs Claudine Monari, Method for the erasure of a static RAM and corresponding integrated circuit memory ,(1998)
Bruce Barbara, Robert A. Abbott, Richard S. Roy, Static ram with high speed, low power reset ,(1988)
Hirofumi Shibuya, Hiroyuki Goto, Fumio Hara, Shigemasa Shiota, Kinji Mitani, Nonvolatile memory system ,(2006)
Jun Kajiwara, Shiro Sakiyama, Katsuji Satomi, Hiroo Yamamoto, Katsuhiro Ootani, Masayoshi Kinoshita, Power circuit including inrush current limiter, and integrated circuit including the power circuit ,(1999)
Jeffrey E. Smith, Roshan J. Fernando, Keng L. Wong, Gregory F. Taylor, Power-on initializing circuit ,(1997)
Charles Roth, Amit Dor, Programmable power transition counter ,(2004)