Central processing unit with hardware controlled checkpoint and retry facilities

摘要: A data processing system with a central unit (CPU), main store (MS), and high speed storage (HSS) interposed between the CPU store. The CPUhas degree of overlap pipelining. That is, plurality instructions are buffered predecoded through several stages prior to issuance individual execution units where further instruction operand buffering takes place. may be highly pipelined, wherein succeeding can issued completion instruction. Additional hardware is added providing ability periodically establish checkpoint which stores minimum amount status information permit proceed cause re-establish all operated on at time was made.