Method and apparatus for a synthesizer architecture
作者： Stephen B. Einbinder , Robert E. Stengel , Jeffrey B. Wilhite
DOI:
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摘要: A synthesizer architecture, responsive to a low noise reference signal from discrete oscillator, provides continuous periodic output with period that is fractional multiple of the signal. One exemplary embodiment includes phase detector providing control selected one plurality integrated voltage controlled oscillators (VCO), wherein sub- harmonic time sampling detector. Another divider input in response an VCO. Yet another comprises injection locked ring oscillator narrow band variable period.
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