Programmable slew rate phase locked loop
作者： Justin Walraven
DOI:
关键词:
摘要: A system includes a first phase-locked loop (PLL) circuit, slew rate limiter and second PLL. The PLL is configured to receive an input signal, generate output identifying frequency associated with the phase information signal. from PLL, determine whether of changing at greater than predetermined rate, signal indicating rate. limiter, angle or based on output.
lens.org 参考文章(17)
Michael Sobelman, Bruno Garlepp, Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference ,(2004)
Stephen B. Einbinder, Robert E. Stengel, Jeffrey B. Wilhite, Method and apparatus for a synthesizer architecture ,(2013)
Robert E. Stengel, Lawrence M. Ecklund, Device and method for phase compensation ,(2009)
Stephen A. Scott, Nam Dang, Tuning module for a dual frequency PLL synthesized tuner ,(1997)
Takuya Takagi, Slew rate calibrating circuit and slew rate calibrating method ,(2006)
Glen A. Myers, Method and apparatus for the cancellation of interference in electrical systems ,(1995)
Jr. William D. Woodward, Rate limited control mechanism for mpeg pcr dejittering ,(2005)
Richard A. Nichols, Digital PLL with conditional holdover ,(2002)
Jerry Chuang, William C. Black, Scott A. Irwin, PMA RX in coarse loop for high speed sampling ,(2007)
Michael Drexler, Ralf-Detlef Schaefer, Switchable PLL circuit ,(2006)