Switching loss analysis considering parasitic loop inductance with current source drivers for buck converters
作者： Zhiliang Zhang , Jizhen Fu , Yan-Fei Liu , P. C. Sen
DOI: 10.1109/APEC.2010.5433426
关键词:
摘要: In this paper, the switching loop inductance was investigated on Current Source Drivers (CSDs). The analytical model developed to predict losses. It is noted that although CSDs can reduce transition time and loss greatly, still has current holding effect CSDs. This results in high turn off for control MOSFET a buck converter. Thus, an improved layout proposed achieve minimum inductance. experimental verified significant reduction owing of converter with 12V input, 1.3V output 1MHz.
sci-hub.se 参考文章(18)
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