Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs

摘要: Non-volatile memories (NVMs) outperform traditional SRAMs in terms of low power consumption, high capacity, near-zero power-on delay, and error-resistance. Researchers have demonstrated the possibilities implementing FPGA building blocks with various types NVMs. However, NVMs also bring several new design challenges to FPGAs: slow write performance NVM may degrade (re)configuration speed, while limited endurance constrains number times that can be (re)configured. Unfortunately, none these features are taken into consideration current synthesis tools, which been optimized solely for SRAM-based FPGAs. To tackle this limitation, we propose make placement process aware costly writes. Our contributions three-fold: We first construct mathematical models characterize reconfiguration costs NVM-based Second, identify three flexibilities exploited reduce cost. Finally, present approaches designers fine-tune balance cost timing routability constraints according their needs. The proposed algorithms incorporated Verilog-to-Routing (VTR) CAD tool. Experiments on standard MCNC benchmark circuits show our approach eliminates up 67% writes during process, thus effectively improving