Runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs

摘要: Field Programmable Gate Array (FPGA) has been widely adopted as modern reconfigurable computing platforms. Traditionally, the storage elements in FPGAs are static RAM (SRAM), which large leakage power and limited scalability. Recently, non-volatile memory (NVM) is proposed to replace SRAM FPGA systems for density considerations, at cost of inducing larger dynamic power. Hybrid combine advantages NVM by employing both logic elements. Although feasibility hybrid confirmed, design flow not fully explored features yet, resulting inferior system performance. Besides, traditional does consider reconfiguration cost, may prolong procedures thus degrade performance dynamically systems. This work proposes a runtime dual aware placement strategy architecture. The scheme considers tradeoff between latency optimizes overall system. Evaluation shows that improves 14.6% SRAM-MRAM compared with default strategy.