Built-in self at-speed delay binning and calibration mechanism in wireless test platform

摘要: An at-speed BIST delay testing technique is proposed. It differs from traditional circuit speed techniques by changing the system clock rate. This method supplies test pattern to using lower-speed frequency, then applies internal adjust edge for and binning. The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment with high-precision (28ps) calibration proposed performance contribution of this work proposal a feasible technique. Test chip DFT strategies are fully validated instruments HOY wireless system.