Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi2 tunnel junctions
作者： L. Knoll , Q. T. Zhao , S. Trellenkamp , A. Schafer , K. K. Bourdelle
DOI: 10.1109/ESSDERC.2012.6343356
关键词:
摘要: Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained unstrained SOI with shallow doped Nickel disilicide (NiSi 2 ) source drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly easies their fabrication by tilted dopant implantation using high-k/metal gate as shadow mask segregation. Two methods of segregation are compared: Dopant based “snow-plough” dopants during silicidation into silicide (IIS) followed thermal outdiffusion. High drive currents up 60 μA/μm planar p-TFETs were achieved indicating good silicide/silicon junctions. The non linear temperature dependence inverse subthreshold slope S indicates typical TFET behavior. Strained Si NW array n-TFETs omega shaped HfO /TiN gates showed high 7 @ 1V V dd steep slopes minimum values 50mV/dec due smaller band gap optimized electrostatics.
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