Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
作者： Fuji Yang , Jay O'Neill , Patrick Larsson
DOI:
关键词:
摘要: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as serdes receiver. In one embodiment, includes:(1) central frequency synthesizer to provide both in-phase quadrature-phase clock signals (2) plurality channel-specific receivers coupled synthesizer. Each is receive deserialize data signal include recovery having phase detector interpolator. The interpolator from couple
google.de 参考文章(13)
Fumio C O Mitsubishi Denki K.K. Ishizu, Clock recovery circuit of demodulator ,(1993)
Deog-Kyoon Jeong, Kyeongho Lee, Single chip CMOS transmitter/receiver ,(2001)
Donald R. Laturell, Baiying Yu, Peter C. Metz, Clock and data recovery with extended integration cycles ,(2002)
A. Younis, B. Das, C. Boecker, Yiqin Chen, K. Hossain, S. Irwin, B. Grung, M. Robinson, F. Abughazaleh, A low jitter, low power, CMOS 1.25-3.125Gbps transceiver european solid-state circuits conference. pp. 121- 124 ,(2001)
Mark Alan Horowitz, Wingyu Leung, Delay stage circuitry for a ring oscillator ,(1994)
Iradj Shahriary, Kevin M. Mcnab, Phase-locked loop frequency tracking device including a direct digital synthesizer ,(1991)
Konstantin A. Meshkovsky, Alexander G. Sokolov, Franklin S. Miller, Vladimir J. Arkhipkin, Method and apparatus for increasing spectral efficiency of cdma systems using direct sequence spread spectrum signals ,(1999)
Hans J. Kunz, Johannes H. A. Brekelmans, Johannes S. Vromans, Receiver having narrow bandwidth phase-locked loop demodulator ,(1998)
Haw-Jyh Liaw, Donald V. Perino, Spread spectrum clocking of digital signals ,(1999)
Wilhelm Hegeler, Radio data signal demodulator with clock signal recovery ,(1994)