A low jitter, low power, CMOS 1.25-3.125Gbps transceiver
作者： A. Younis , B. Das , C. Boecker , Yiqin Chen , K. Hossain
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摘要: This paper describes a high-speed CMOS transceiver that can run at rate of up to 3.125Gbps, from 1.8V power supply. The chip includes 10/20:1 full duplex Serializer/Deserializer, (SERDES), novel clock and data recovery circuits, differential I/Os. Special techniques have been used increase the jitter tolerance as well reduce amount output jitter. has fabricated in TSMC 0.18µ 1P6M digital process consumes less than 175mW when running 2.5Gbps with 26ps deterministic 3.9ps random
参考文章(3)
Bernard L. Grung, Moises E. Robinson, Phase lock loop and transconductance circuit for clock recovery ,(1998)
A. Fiedler, R. Mactaggart, J. Welch, S. Krishnan, A 1.0625 Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis international solid-state circuits conference. pp. 238- 239 ,(1997) , 10.1109/ISSCC.1997.585369
P. Larsson, Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 574- 576 ,(1997) , 10.1109/4.563679