Double word fetch system

摘要: A memory subsystem couples to a single word bus in common with central processing unit for requests received therefrom. The includes at least pair of independently addressable dynamic module units. Each number rows random access (RAM) chips. receives as part each request an address, the significant portion which specifies row chips be accessed within first one further control circuits, timing circuits and addressing circuits. couple both units provide required address signals modules enabling simultaneous words response predetermined type operation, condition generate sequence read out into tri-state operated data registers. outputs registers are connected under multiplexed onto transfer over corresponding successive cycles.