Memory control circuit that selectively performs address translation based on the value of a road start address
作者： Susumu Yamada
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摘要: A memory control circuit improves the read speed of a program stored in ROM. The includes divided into four blocks, an address translation for providing 4N+1 to blocks 0 and 1 only when required is 4N+2 or 4N+3, set latch circuits latching data from each selector selecting necessary among latched outputting it bus. Accordingly, three more are made readable every operation.
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