Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process

摘要: A process for integrating the fabrication of a thick, copper inductor structure, with narrow channel length CMOS devices, has been developed. The integrated features use only one additional photolithographic masking step, used to form opening in an IMD layer, that will accommodate subsequent structure. After forming damascene type openings same region, is deposited and then defined, result first region semiconductor substrate, as well interconnect structures, located second devices. equal thickness results increased inductance, or quality factor, when compared counterparts formed thinner metal inductors.