Conditional-Sum Addition Logic

摘要: Conditional-sum addition is a new mechanism for parallel, high-speed of digitally-represented numbers. Its design based on the computation ``conditional'' sums and carries that result from assumption all possible distributions various groups columns. A rapid-sequence mode operation provides an rate invariant with lengths summands. Another advantage possibility realizing adder ``integrated devices'' or ``modules.'' The logic conditional-sum applicable to positive radices, as well multisummand operation. In companion paper, comparison several adders shows that, within set stated assumptions, superior in certain respects, including processing speed.