Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
作者： Nitin V. Sarangdhar , James M. Brayton , Michael W. Rhodehamel , Glenn J. Hinton
DOI:
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摘要: A computer system, and a method performed by it, having mechanism for ensuring consistency of data among various level(s) caching in multi-level hierarchical memory system. The cache includes an external bus request queue which associated mechanism, cooperate to monitor control the issuance requests, such as read requests write onto bus. system one or more CPUs each this mechanism.
google.com.br 参考文章(6)
Terry L. Lyon, Dual pipe cache memory with out-of-order issue capability ,(1991)
Emil W. Brown, Joseph A. Petolino, Cache memory arrangement with write buffer pipeline providing for concurrent cache determinations ,(1993)
Michael A. Callander, Douglas E. Sanders, Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol ,(1990)
Rebecca L. Stamm, John Edmondson, Raymond Strouble, David Archer, Samyojita Nadkarni, Processor system with writeback cache using writeback and non writeback transactions stored in separate queues ,(1993)
V. Popescu, M. Schultz, J. Spracklen, G. Gibson, B. Lightner, D. Isaman, The Metaflow architecture IEEE Micro. ,vol. 11, pp. 10- 13 ,(1991) , 10.1109/40.87564
Robert Sidney James, Eugene Joseph Annunziata, Kwang Gun Tan, Data processing system having at least two with a fast memory-equipped processors ,(1978)