Hto offset for long leffective, better device performance

摘要: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory are provided. The contain two or more cells on a semiconductor substrate bit line dielectrics between cells. cell contains charge trapping dielectric stack, poly gate, pair pocket implant regions, lines. can be formed by process at higher energy level concentration dopants without suffering device short roll off issues because spacers sidewalls constrain in narrower regions.