CT-NOR differential bitline sensing architecture

摘要: Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of transistors arranged electrically in serial configured to control gate voltage pass transistor. The transistor, turn, enables current flow between two metal bitlines the architecture. Accordingly, relative or can be measured and utilized determine program erase state transistor transistors. particular with small capacitance chosen resulting fast correspondence voltage/current current. This equate times array, based on differential sensing bitlines.