作者: Paul Edward Movall , William Joseph Armstrong , Charles Scott Graham , Shawn Michael Lambeth , Thomas Rembert Sand
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摘要: An interrupt and message batching apparatus method reduces the number frequency of processor interrupts resulting context switches by grouping I/O completion events together with a single in manner that balances operation latency requirements utilization to optimize overall computer system performance. The invention sends from complex an adapter on bus commanding device connected perform function. Upon commanded function, generates it bus. is enqueued queue memory, count updated, signalled if when exceeds pacing count. A signalling timer may also be programmed fast response time value has relatively high or slow low latency. started then elapsed.