Dry etch challenges of 0.25 /spl mu/m dual damascene structures

摘要: Interconnects for integrated circuits are generally formed by reactive ion etching (RIE) of the metal stack. However, this process is susceptible to shorts between neighboring lines due either incomplete stack or electrically conducting etch products. As a result, there has been much recent interest in using damascene processes (where chemical-mechanical polishing (CMP) used form lines) fabricate interconnects at dimensions 0.25 /spl mu/m and less. The number benefits; defined oxide RIE, which considerably simpler than RIE multilayer CMP provides nearly planar surface, eliminating need good gap fill interlevel dielectrics. Finally, vias can be combined into one step (i.e. dual damascene), resulting reduced cost.