Power reducing buffer/latch circuit
作者： Wingcho Fung , Krishna M. Yellamilli
DOI:
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摘要: A data latch/buffer cell for driving a bus line conditionally precharges the only during cycles prior those in which is actually sampled. An input gate selectively enables signal application to latching circuit. Prior of input, conditional precharge applied latch circuit clear previously latched data. coupled pull-down transistor drives bus. The also complementary pull-up line. Application delayed relative turning off preclude rush through current driver.
google.de 参考文章(6)
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