High performance multifunction direct memory access (DMA) controller
作者： Jianhua Pang
DOI:
关键词: Wait state 、 CPU multiplier 、 Clock signal 、 Direct memory access 、 Computer hardware 、 Computer science 、 Transfer (computing) 、 Controller (computing) 、 Back-side bus 、 Central processing unit
摘要: A direct memory access (DMA) controller having to data transfer capability, a programmable fixed priority scheme, wait state, buffer chaining mode cascade-master mode, separate channels for internal and external devices, 8 or 16 bit requester bus size. The DMA includes channel circuit connected from port, CPU interface, the interface therebetween, state machine which generates clock signal that is used transferring across delays of preprogrammed number cycles, register setting cycles.
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