Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocols

摘要: A design structure for a processor system may be embodied in machine readable medium designing, manufacturing or testing integrated circuit. The embody circuit including multiple processors with respective cache memories. specify enhanced coherency protocols to achieve memory integrity multi-processor environment. describe bus controller manages interfaces master devices and slave devices. also I/O device that couple directly the while couples via controller. In one embodiment, blocks partial responses it receives from all except being included combined response sends over buses.