Delay circuit for gate-array lsi
作者： Shigeru Fujii , Masanori Oozeki
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摘要: A delay circuit for a gate-array LSI including at least one in- ver t er having plurality of P-channel transistors (Qip to Q 4 p) and N-channel (Q 1n 4n ) connected in series. The P-channel/N-channel are driven by an input potential (IN), the common output innermost pair p, Q4 n) generates (OUT).
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