Write strobe generator for clock synchronized memory.

摘要: An on-chip memory control circuit generates a proper WRITE STROBE signal for clock synchronized pipe-line operated integrated memory. A symmetrical having half the frequency of system is produced by applying to C input standard master slave delay type flip-flop (2) its Q output fed back D input. negative going pulse train O/p comprising at every transition generated level change detector (4-24) which issues desired width whenever detected. delayed O/PD (26) delaying phip an amount depends on speed and other design criteria. The trains are applied asynchronous (30), corresponds signal.