Differential controlled delay elements and skew correcting detector for delay-locked loops and the like

作者: Jeffrey L. Sonntag

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摘要: A fully differential variable delay element for providing precision delays use in digital phase-locked loops or the like. The each stage is controlled by changing bias currents and coupling of a capacitance load thereto, therby reducing sensitivity to electrical noise at low current levels (long times). Included circuit which substantially removes any skew differentially delayed signals from element.

参考文章(4)
D.K. Jeong, G. Borriello, D.A. Hodges, R.H. Katz, Design of PLL-based clock generation circuits IEEE Journal of Solid-State Circuits. ,vol. 22, pp. 255- 261 ,(1987) , 10.1109/JSSC.1987.1052710