Data synchronization device

摘要: A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock (CLKO). In case of binary signal, the includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated logical level and counting number successive 1's 0's respectively. These produce count including counted bits their level. The further decoder (DEC) generating in synchronism (CLKO) which is function numbers. generated constitute requested (OUT). data delay module (DEL) for deriving from input (CLKI) received (IN), three intermediate signals (OA-OC) shifted phase respect other controlling one set counters (CA1-CC1; CA0-CC0) included systems. latter also include majority voting (MAJ1; MAJ0) reading numbers by corresponding set, comparing these selecting subset at least having same bits. assumed be correct therefore transferred (DEC).