Test pattern structure for endurance test of a flash memory device
作者： Hee Youl Lee
DOI:
关键词:
摘要: This invention relates to a test pattern structure comprising for endurance of flash memory device comprising: at least three active regions formed on semiconductor substrate, each region being isolated by field oxide film; common drain region, respectively; source left and right sides the in first floating gate along side region; second control overlapped with gates, respectively connected from other both ends gates; select over metal wires respectively.
lens.org 参考文章(2)
Radu Barsan, Jonathan Lin, Control gate-addressed cmos non-volatile memory cell that programs through gates of cmos transistors ,(1996)
Katsuya C O Intell.Property Div. Sakai, Ultraviolet-erasable type nonvolatile semiconductor memory device having asymmetrical field oxide structure ,(1991)