Scalable dual-bit flash memory cell and its contactless flash memory array

摘要: A scalable dual-bit flash memory cell of the present invention comprises a gate region having pair floating-gate structures with select-gate being formed therebetween and planarized control/select-gate over second gate-dielectric layer or without sidewall dielectric spacers floating gates; conductive bit line together first spacer flat bed by source/drain diffusion etched raised field-oxide layers. contactless array plurality bit-lines transversely to parallel STI regions word lines integrated control-gate/select-gates described cells patterned bit-lines.