On the Scalability of Parallel Verilog Simulation

摘要: As a consequence of Moore’s law, the size integrated circuits has grown extensively, resulting in simulation becoming major bottleneck circuit design process. Consequently, parallel emerged as an approach which can be both fast and cost effective. In this paper, we examine performance Verilog simulator on four large, real designs. previous work made use either relatively small benchmarks or synthetic circuits, these is far more realistic. We develop parser for files enabling us to simulate all synthesizable circuits. utilize our test benches; LEON Processor with 200k gates, OpenSparc T2 processor 400k gates two Viterbi decoder 100k 800k respectively. The makes XTW knowledge first parse files. observed 4,000,000 events per second 32 processors gates. simulators’ was shown scalable.