A Simulated Annealing Technique for Optimizing Time Warp Simulation

摘要: According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming major bottleneck circuit design process. Parallel and distributed simulations can be applied as fast, cost effective approaches large, complex circuits. In this paper, a simple yet simulated annealing-based approach is proposed optimize choice time window for optimistic parallel simulation. We chose gate level our experimental vehicle. Our results show up 52% improvement using annealing algorithm. To best knowledge, first that SA been performance Time Warp simulations.