Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
作者： Marc Boule , Zeljko Zilic
DOI: 10.1109/ASPDAC.2007.358006
关键词:
摘要: In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used assertion-based verification (ABV) languages. A generator capable transforming assertions into efficient allows adoption ABV in hardware emulation. Towards that goal, introduce algorithms sequence fusion and length matching intersection, two SERE operators are not typically used over expressions. We also develop an algorithm failure detection automata, concept critical to extending ABV, as well our symbol encoding. Experiments with complex show tool outperforms best known generator.
computer.org
ieeecomputersociety.org参考文章(10)
Pascal Raymond, Recognizing Regular Expressions by Means of Dataflow Networks international colloquium on automata languages and programming. ,vol. 1099, pp. 336- 347 ,(1996) , 10.1007/3-540-61440-0_140
R. Sidhu, V.K. Prasanna, Fast Regular Expression Matching Using FPGAs field-programmable custom computing machines. pp. 227- 238 ,(2001) , 10.1109/FCCM.2001.22
Rajeev Motwani, John E. Hopcroft, Jeffrey D. Ullman, Rotwani, Introduction to Automata Theory, Languages, and Computation ,(1979)
Andrew Seawright, Forrest Brewer, High-level symbolic construction technique for high performance sequential synthesis Proceedings of the 30th international on Design automation conference - DAC '93. pp. 424- 428 ,(1993) , 10.1145/157485.164961
Marcio T. Oliveira, Alan J. Hu, High-level specification and automatic generation of IP interface monitors design automation conference. pp. 129- 134 ,(2002) , 10.1145/513918.513952
Yael Abarbanel, Ilan Beer, Leonid Gluhovsky, Sharon Keidar, Yaron Wolfsthal, FoCs: Automatic Generation of Simulation Checkers from Formal Specifications computer aided verification. pp. 538- 542 ,(2000) , 10.1007/10722167_40
M. Boule, Z. Zilic, Incorporating efficient assertion checkers into hardware emulation international conference on computer design. pp. 221- 228 ,(2005) , 10.1109/ICCD.2005.66
S.A. Edwards, An Esterel compiler for large control-dominated systems IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 21, pp. 169- 183 ,(2002) , 10.1109/43.980257
Mike Gordon, Joe Hurd, Konrad Slind, Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving Lecture Notes in Computer Science. pp. 200- 215 ,(2003) , 10.1007/978-3-540-39724-3_19
Radu Grigore, CONSTRUCTING CHECKERS FROM PSL PROPERTIES international conference on control systems and computer science. ,vol. 2, ,(2005)