Debug enhancements in assertion-checker generation

摘要: Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use silicon debug has been limited so far. A set of techniques with either pre-silicon or post-silicon scenarios discussed. Presented features such as assertion threading, activity monitors, cover counters completion mode assertions. The common goal these checker enhancements is to provide better more diversified ways achieve visibility within circuits, which, turn, lead efficient circuit debugging. Experimental results show that modifications can be done modest hardware overhead.