An enhanced debug-aware network interface for Network-on-Chip

摘要: As emerging System on Chips (SoCs) tend to have many cores, the interactions among cores through functional interconnects such as bus or Network (NoCs) are becoming complex. The increase in complexity of IP blocks and on-chip communication has accentuated need enhance traditional debug methods for SoCs. In this paper, we propose a new aware Interface (NI). proposed NI monitors transactions issued by processing elements extracts global order from local partial transactions. Moreover, interface provides mechanism cross-triggers debugging. modules charge cross-trigger debugging monitor connected invoke appropriate operations at right time. Trace data trigger events extracted routed Shared Direct Memory Access Unit (SDMAU). SDMAU combines traces different NIs. major benefits using our over techniques follows: 1) can generate non-intrusively states system that involve multiple clock domains enable validation properties, 2) It detect, mark bypass severe faulty conditions deadlocks resulting design errors electrical faults real time, 3) maintains an efficient transfer trace external memory there is no large internal memory.